1. Field of the Invention
The present invention relates to a highly efficient voltage boosting circuit.
2. Description of the Related Art
A voltage boosting circuit is a circuit frequently used for generating another voltage from a power supply voltage, and more specifically the higher voltage than the power supply voltage. Generally, in the voltage boosting circuit, a capacitance element is charged from the power supply so that the output voltage is increased. Accordingly, the voltage boosting circuit can generate a boosted voltage having an absolute value greater than a power supply voltage Vcc.
A conventional example of the voltage boosting circuit will be described in more detail with reference to FIG. 1 and FIGS. 2A to E.
The conventional voltage boosting circuit is composed of N-channel transistors N5-1 to N5-8 and capacitors CP5-1 to CP5-8. Clock signals CK5-1 to CK5-4 are supplied to the voltage boosting circuit. A terminal OUT-5-1 is an output terminal for outputting the boosted voltage.
The operation of the voltage boosting circuit shown in FIG. 1 will be described with reference to FIGS. 2A to E. Referring to FIGS. 2A to E, when the clock signal CK5-2 goes to a high level in the state in which the clock signal CK5-3 is at a low level as shown in FIG. 2C, the voltage at the gate of the transistor N5-5 is boosted to a level sufficiently higher than the power supply voltage Vcc through the operation of the coupling capacitor CP5-1. This allows the capacitor CP5-5 to be charged to the power supply voltage Vcc. At this time, the clock signal CK5-4 is at low level so that the transistor N5-6 remains turned off. Therefore, no change is transferred through the transistor N5-6.
Then, the clock signal CK5-2 goes to the low level to turn off the transistor N5-5. As the clock signal CK5-3 goes to the high level, the potential of the capacitor CP5-5 is increased to the potential equal to twice of the power supply voltage Vcc when a loss caused by parasitic capacitance is negligible.
While the boosted level is maintained, the clock signal CK5-4 goes to the high level so that the transistor N5-6 is turned on. At this time, the clock signal CK5-1 held at the low level. Thus, the voltage at the gate of the transistor N5-6 is increased to a level higher than the power supply voltage. As a result, the charge stored in the capacitor CP5-5 is transferred to the capacitor CP5-6. The voltages of the capacitors CP5-7 and CP5-8 are boosted in the same manner as described above, and the boosted voltage is finally outputted from the terminal OUT5-1.
As described above, if any loss caused by parasitic capacitance is negligible, the voltage boosting circuit can boost the input voltage to (the number of capacitance elements plus one) multiplied by the power supply voltage Vcc. Similar to the boosting operation of a positive voltage, the input voltage can be boosted in a negative direction.
However, in the above conventional voltage boosting circuit there are some problems in that current consumption is much and the boosting operation is slow. Particularly, the problems are severe when the output terminal is linked to a load capacitor. Such a case will be described below referring to FIG. 1.
As the output terminal is linked to a large load capacitor, the voltage at the output terminal OUT5-1 cannot be rapidly increased to a desired voltage even if the boosting operation is repeated. In this case, the voltage between the source and the drain in each of the switching elements (the transistors N5-5 to N5-8) is hardly increased. Accordingly, the voltage at the output terminal continues to be lower than the boosted voltage by the capacitance elements (the capacitor CP5-5 to CP5-8) of the four stages. In this state, therefore, driver elements for driving the clock signals CK5-3 to CK5-1 ill consume the current in vain. More specifically, while the voltage at the output terminal OUT5-1 is as low as the power supply voltage Vcc, three of the boosting capacitance elements (the capacitor CP5-5 to CP5-8) are unnecessary and will only increase the current consumption.
For the purpose to overcome the above problems, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-111095). In this reference, the efficiency of power usage is improved when the output voltage is low, so that the time of the boosting operation is shortened. The voltage boosting circuit is composed of booster cells and a switching circuit for switching the connection of the booster cells. The switching circuit is arranged between the booster cells. The booster cells are grouped into groups. The switching circuit connects the groups to the output terminal in parallel. In each group, one or more booster cells are connected in series. The number of booster cell groups, and the number of booster cells in the group are variable.
However, in the voltage boosting circuit disclosed in the above reference, the booster cells and the switching circuit are separately provided. Accordingly, the current consumption is still abundant.
In conjunction with the above description, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-179264). In this reference, the voltage boosting circuit is composed of a plurality of boosting blocks, switches, a voltage determining section and a circuit selecting section. Each of the plurality of boosting blocks is composed of a plurality of diodes connected in series between a power supply voltage input terminal and a boosting voltage output terminal or a circuit equivalent to the plurality of diodes, and a capacitor connected to a node between every two of the plurality of diodes. A desired boosted voltage is produced through a forward direction charge transfer operation by the diodes and the capacitors. The switches are provided between the power supply voltage input terminal and the boosting blocks, respectively. The voltage determining section determines an input voltage level at the power supply voltage input terminal. The circuit selecting section controls the switches based on the determining result of the voltage determining section to select ones of the boosting blocks.
Also, a non-volatile semiconductor memory is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-223588). In this reference, a plurality of basic circuit 20 for carrying out a voltage boosting operation is grouped into a plurality of groups. Clock signals xcfx861 and xcfx862 are supplied to each basic circuits 20 of a part of the groups from the start of the voltage boosting operation. The clock signals xcfx861 and xcfx862 are supplied to each basic circuit 20 of another part of the groups after a predetermined time passes since from the start of the voltage boosting operation. The above clock signals xcfx861 and xcfx862 are supplied to each basic circuit 20 of the remaining groups after a further predetermined time passes. Thus, in the non-volatile semiconductor memory which has a voltage boosting circuit, the increase of the chip area is suppressed the to the minimum. Also, the decrease of the boosted voltage can be prevented.
Also, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-110989). In this reference, the voltage boosting circuit has 4-phase clock signal. A drive clock signal is supplied to the gate of a boosting transistor the transistor N1 provided between the gate Q1 and the drain P1 in a charge transfer transistor M1. The drive clock has the same timing as that at a node P2 which is located at a predetermined number of stages from a node P1 in a P2 direction. For example, when the gate of the transistor the transistor N1 is connected with a node P4, the charge transfer efficiency by the transistor the transistor N1 can be improved.
Therefore, an object of the present invention is to provide a voltage boosting circuit of low power consumption.
Another object of the present invention is to provide a voltage boosting circuit which can provided a boosted voltage quickly.
In order to achieve an aspect of the present invention, a voltage boosting circuit includes a plurality of unit circuits provided in parallel, and a control unit. Each of the plurality of unit circuits includes a charge capacitor connected to an anode of a rectifying element or a diode at one end and to a discharge control signal at the other end, and a charge transfer section transferring a charge from the charge capacitor to the charge capacitor of a next one of the plurality of unit circuits in response to a transfer control signal. The last one of the plurality of unit circuits further includes a last rectifying element, and a last capacitor connected to an anode of the last rectifying element at one end and to a discharge control signal at the other end. The charge transfer section in the last unit circuit transfers a charge from the charge capacitor to the last charge capacitor in response to the transfer control signal. Cathodes of a plurality of the rectifying elements and a cathode of the last rectifying element are connected together with each other. The control unit supplies a plurality of the discharge control signal and a plurality of the transfer control signals to the plurality of unit circuits.
Here, the charge capacitors and the last charge capacitor are charged from a power supply. In this case, the one end of each of the charge capacitors and the last charge capacitor is connected to the power supply via at least a rectifying element. Also, each of the plurality of unit circuits further includes a charging section charging the charge capacitor in response to a charge control signal. The control unit further supplies a plurality of the charge control signals to the plurality of unit circuits. In this case, the charging section includes a coupling capacitor connected to the charge control signal at one end, and a transistor which has a gate connected to the other end of the coupling capacitor, a drain connected to the power supply, and a source connected to the one end of the charge capacitor. In this case, the charging section further includes a holding transistor having a gate connected to the one end of the charge capacitor, a drain connected to the power supply, and a source connected to the gate of the transistor.
Also, the charge transfer section may include a coupling capacitor connected to the transfer control signal at one end, and a transistor having a gate connected to the other end of the coupling capacitor, a drain connected to the charge capacitor, and a source connected to the one end of the charge capacitor in a next one of the plurality of charge capacitor. The charging section further includes a holding transistor having a gate connected to the source of the transistor, a drain connected to the one end of the charge capacitor, and a source connected to the gate of the transistor. Also, the charge transfer section may further includes a preset transistor charging the gate of the transistor in response to a preset signal, the preset transistor having a gate connected to the preset signal, a drain connected to the power supply and a source connected to the gate of the transistor.
In another aspect of the present invention, a voltage boosting method is attained by storing charges in charge capacitors; by sequentially transferring the charges to a last one of charge capacitors to boost a voltage of the last charge capacitor; and by subsequently charging the output capacitor component with the charge stored in the last charge capacitor.
Here, the voltage boosting method may further include initially charging an output capacitor component with the charges stored in the charge capacitors.
Also, the initially charging may be attained by supplying a bias voltage to the charge capacitors.
Also, the sequentially transferring may be attained by intermediately charging the output capacitor component with the charge stored in each of the charge capacitors while sequentially transferring the charges to the last charge capacitor.
Also, the sequentially transferring may be attained by supplying a bias voltage to a current one of the charge capacitor; and by removing the bias voltage from a next one of the charge capacitors.
Also, the subsequently charging may be attained by supplying a bias voltage to the last charge capacitor.
Also, the voltage boosting method may further include: charging the output capacitor component using a power supply voltage previous to the initial charging.